FPGA Modeling and Optimization of SIMON Block Cipher Design
Submitted by:
Reem Wajdi Jaffal
A Thesis Submitted to the College of Graduate Studies in Partial Fulfillment of the Requirements for Master›s
Degree in: Computer Engineering
Supervised by:
Dr. Sa›ed Abed
Dr. Bassam Jamil Mohd (Co-Supervisor)
Abstract
Security of sensitive data exchanged between devices is an essential requirement, as it provides the needed authentication, confidentiality and privacy. Ciphers, which are encryption algorithms, form the basic mechanisms to implement security. Recently, Low-Resource Devices (LRDs) are increasingly becoming ubiquitous. These devices include RFID tags, wireless sensor nodes, smart cards, Internet of Things (IoTs) and health-care devices. LRDs are designed for constrained environments where cost, power, energy supply and area are limited. With continued scaling of transistor devices, energy and power are becoming the most critical design issues for LRDs. Communication between these devices requires providing adequate level of security without straining the limited resources. Lightweight block ciphers are targeted for LRDs. They balance the required security and minimal resource overhead. Lately, there are several lightweight block ciphers proposed, implemented and optimized in hardware and software platforms. SIMON is one of the lightweight block ciphers that was proposed by National Security Agency (NSA) for the aim of fulfilling the demand for secure, flexible, and analyzable lightweight block ciphers. Compared with other lightweight ciphers, SIMON exhibits good hardware performance metrics. Most of published studies for SIMON cipher addressed area optimization. Unfortunately, despite their importance, little attention was given to energy and power optimization. The objective of this study is to implement, optimize and model SIMON design metrics. Our emphasis is to optimize the most critical resources for LRDs, namely energy and power. Various implementations are examined. An optimization metric combining several metrics is defined. The optimum implementation is then determined. The targeted hardware platform is FPGA as it provides many advantages, such as speed, configurability, flexibility and low cost development effort. Our study shows that scalar implementations require 39% less resources and 45% less power consumption compared with pipelined implementations. On the other hand, pipelined implementations demonstrate 12 times higher throughput and consume 31% less energy compared with scalar ones. Moreover, the most energy-efficient design and the optimum one is 2-rounds pipelined implementation, which consumes 31% of the best scalar implementation energy. While the best design in terms of area is 1-round scalar implementation.
الكاتب : المجلة || عدد الزوار : (55) || طباعة الموضوع
